Atul Sharma

Atul Sharma

PhD, Electrical & Computer Engineering, Purdue University
Federated and decentralized machine learning: robustness, privacy, personalization

I advance collaborative machine learning where many nodes jointly train models without sharing raw data. I was advised by Prof. Saurabh Bagchi and Prof. Somali Chaterji, with theoretical collaboration from Prof. Chaoyue Liu.

NeurIPS 2026Tiered Gossip Learning, accepted
US Patent ApplicationCollaborative federated learning, published Jan 2026
IEEE S&P · CVPR · AsiaCCSPeer-reviewed security and ML venues
ICML 2026 Silver ReviewerTop-tier reviewer designation

Research

My research focuses on collaborative machine learning, where multiple nodes jointly train models without sharing raw data. My early work studied Byzantine-robust aggregation in federated learning, where a central server coordinates collaboration. I then explored improving model mixing and convergence under communication constraints in distributed settings. My current work investigates fully decentralized learning protocols that let nodes autonomously discover and collaborate with peers with similar data distributions, improving personalization in non-IID environments.

Personalization in Decentralized Learning Under review, ICLR 2026

Aug 2025 – present
  • Designed a decentralized P2P protocol that learns the latent statistical topology of non-IID networks via social triangulation, where nodes share ranked neighbor lists and train per-node embeddings with a ladder triplet loss.
  • Matches validation-based baselines without a server, validation data, or cluster priors, using a four-slot explore–exploit sampler and a tent-weighted warmup anchor for stable affinity estimation.

Tiered Gossip Learning (TGL) Accepted, NeurIPS 2026

Jan 2023 – May 2026
  • Introduced a hybrid two-layer push-gossip-pull topology that achieves dense global model mixing and scalability by offloading aggregation to a dynamic relay backbone.
  • Showed through theory and experiments that TGL matches the convergence rate of decentralized local SGD while cutting communication cost by up to 80% on non-IID vision and language tasks.

Byzantine-robust Federated Learning (FLAIR) · paper · code

Mar 2020 – Aug 2022
  • Developed an aggregation defense against model poisoning based on a novel statistic, the flip-score, to identify malicious clients.
  • Evaluated against multiple models and datasets and against an adaptive whitebox attacker with full knowledge of the defense.

Lerna: Language-model Tuning of Genomic Error Correction · paper · code

Aug 2019 – Jun 2020
  • Built a framework that adapts non-directional Transformers to configure genomic error-correction tools, with an 18x inference speedup over state-of-the-art RNN models.
  • Removed the need for a reference genome by using perplexity as a fitness measure, staying within 0.31% of the theoretical optimum alignment rate on Illumina and Nanopore datasets.

Publications & Patent

Full list with citation counts on Google Scholar.

Industry Research & Engineering

Google · Software Engineering Intern

Jun – Aug 2023 · Sunnyvale, CA
  • Trained ML models on telemetry to estimate SSD flash wear-out, extending hardware lifespan in Google data centers.
  • Built an end-to-end data pipeline reaching 80% precision and 90% recall in predicting critical bad-block growth.

NVIDIA · Applied Power Architecture Intern

Jun – Aug 2022 · Santa Clara, CA
  • Implemented Implicit Q-Learning to automate CPU/GPU operating-point selection under power limits.
  • Achieved a 16x inference speedup with no accuracy loss by replacing existing ML models with an optimized RL agent.

NVIDIA · Applied Power Architecture Intern

May – Aug 2021 · Santa Clara, CA
  • Extended Dynamic Boost 2.0 to non-graphics workloads to optimize power allocation between the CPU and GPU.
  • Developed a sequence alignment algorithm to identify identical workloads across operating points, building a high-fidelity dataset for performance prediction.

NVIDIA · ASIC Engineer Intern

May – Jul 2018 · Bengaluru, India
  • Built a generic sequence monitor and custom testbench to verify power-gating features in GPUs, then integrated it into the full-chip testbench.

Education

Purdue University · Ph.D., Electrical and Computer Engineering

Aug 2019 – Aug 2026

West Lafayette, IN · GPA 3.8/4.0

IIT Kharagpur · B.Tech., Electronics & Electrical Communication Engineering (Honors)

Jul 2015 – May 2019

Minor in Computer Science · GPA 9.4/10 (minor 9.3/10)

Recognition: Silver Reviewer designation, ICML 2026, awarded by Area Chairs for review quality and rigor.

Data Security & PrivacySecurity AnalyticsDistributed Computing Systems Computer Network SystemsFault Tolerant Computer System Design Artificial IntelligenceOperating SystemsMachine LearningDeep Learning